1. Field of the Invention
The invention relates to an FED structure, particularly to an FED cathode plate with an internal via and the fabrication method for the cathode plate, which uses the vaporization to form the internal via such that the cathode sealing area of FED appears homogeneous, thereby increasing the yield.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a typical FED cathode plate. In FIG. 1, the FED cathode plate is generally formed by layers successively deposited onto a substrate 10. The layers include a resistive layer 11, a cathode conductor layer 13, a microtip 2, a microtip cavity 3, a microtip hole 4, a gate line 5, a contact 7, a dielectric layer 16, a tape line 18, a seal 8, and an anode plate 9.
As shown in FIG. 1, in such a structure, the FED emits electrons induced by the electrical field of the gate line 5 from the microtip 2 through the hole 4. The emitted electrons are conducted and sped up by the anode plate 9 and impact the fluorescent powder (not shown) distributed on the surface of the anode plate 9. Thus, fluorescent light is emitted. The light can pass through the anode 9 and present on the back of the anode 9 (i.e. display plate (not shown)) to display an image. The operation principle of the FED is generally similar to a Cathode Ray Tube (CRT), except that the FED can be produced in a thin flat panel display.
A typical FED cathode plate is prepared through 6 photolithography, 6 etchings, and 6 thin film processes. Like numbers refer to like components in all drawings. FIG. 2 is a diagram of the fabrication steps of FIG. 1. In FIG. 2, the steps include deposition, etching, evaporation, and lift-off. As shown in FIG. 2, the FED cathode plate is successively deposited onto a substrate 10 to constitute the layers having a microtip hole 4 on the top, as shown in FIG. 2a. As shown in FIG. 2b, the dielectric layer 16 is etched to form the microtip cavity 3 about 2 xcexcm wide, using dry and wet etching. As shown in FIG. 2c, graze evaporation is used on the plate with a slope of 20xc2x0 to form an aluminium conductor layer 19. As shown in FIG. 2d, the evaporation is used in the plate with a vertical position like the arrow shown to form the microtip 2 within the microtip cavity 3. As shown in FIG. 2e, the phosphoric acid solution is used to lift off excessive deposition, including the layer 19, and only leave the microtip 2 within the cavity 3. Thus, a typical cathode plate is completed. Further, a glass frit is used to join the cathode plate to the anode plate 9 which are then sealed to form an electrode in vacuum.
The sealing area of the electrode is located around the light-emitting region of the display (FIG. 1). The sealing prevents outside air from diffusing into the display, thus ensuring the integrity of the display""s vacuum. The glass frit, however, has a tendency toward corruption. Accordingly, chromium (Cr) is used in the passages (i.e. tape line 18) of the two lateral edges through which the glass frit passes. Although the chromium can prevent corruption from the glass frit, the adhesion difference between chromium and the SiO2 composing the dielectric layer 16 can easily cause splits in the edge of the structure during durability testing of the product, compromising the vacuum inside the display. In such cases, the display provides uneven illumination and a friable structure in the sealed area, thus reducing the yield. As well, the hole 4 is small, about 1 xcexcm, and the efficient depth of focus (DOF) for photolithography is low, so that exposure uniformity may be insufficient, further causing stepper shots"" marks, reducing the yield of the cathode plate.
Accordingly, an object of the invention is to provide an FED cathode plate with an internal via, which prevents diffusion of outside air from corrupting the vacuum inside, thus increasing the evenness and durability of the FED frame.
Another object of the invention is to provide a fabrication method for the FED cathode plate with an internal via, which uses the internal via and improves the processes, thereby reducing the cycle, the limit, and the cost in the processes.
The invention is an FED cathode plate with an internal via and the fabrication method for the FED cathode plate. The FED cathode plate with an internal via includes: a substrate; a resistive layer with a cathode conductor deposited over the substrate; a tape line located on the substrate and kept separate from the resistive layer; a first dielectric layer, located on the resistive layer and part of the tape line and having a microtip cavity to accommodate a microtip; a first gate line, located over the first dielectric layer and having a respective microtip hole of the microtip; an internal via, located on the tape line and abutted against the first dielectric layer and the gate line; a second dielectric layer, located on the tape line and abutted against the internal via, thereby connecting to an anode by an adhesive; a second gate line, located on the second dielectric layer and abutted against the internal via; a metal layer covering the first gate line, the internal via, and the second gate line; and a contact, located on the tape line and connected adjacent to the second dielectric layer, thereby electrically connecting a lead to the outside. The fabrication method includes the following steps: depositing an FED cathode structure from bottom to top including a substrate, a resistive layer, a dielectric layer, and a gate line; dry etching the cathode structure to form a cathode plate with the hole and cavity of a microtip, an internal via, and a contact; sloping the plate to a predetermined angle to form a metal layer by evaporation; forming a microtip within the microtip cavity by vertical layer evaporation; and lifting off the excessive deposition on the surface of the plate by immersing the plate in a chemical solution.